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quadruple associative Instruction Cache 32 KByte,128-entry TLB-4K, 7 TLB-2/4M per thread
Prefetch Buffer (16 Bytes)
Predecode & Instruction Length Decoder
Instruction Queue18 x86 InstructionsAlignmentMacroOp Fusion
ComplexDecoder
SimpleDecoder
SimpleDecoder
SimpleDecoder
Decoded Instruction Queue (28 µOP entries)
MicroOp Fusion
LoopStreamDecoder
2 x Register Allocation Table (RAT)
Reorder Buffer (128-entry) fused
2 xRetirementRegisterFile
Reservation Station (128-entry) fused
StoreAddr.Unit
AGU
LoadAddr.Unit
AGU
StoreData
MicroInstructionSequencer
256 KByte8-way,64 ByteCacheline,privateL2-Cache
512-entryL2-TLB-4K
Integer/MMX ALU,Branch
SSEADDMove
Integer/MMX ALU
SSEADDMove
FPADD
Integer/MMX ALU,2x AGU
SSEMUL/DIVMove
FPMUL
Memory Order Buffer (MOB)
octruple associative Data Cache 32 KByte,64-entry TLB-4K, 32-entry TLB-2/4M
BranchPredictionglobal/bimodal,loop, indirectjmp
128
Port 4
Port 0
Port 3
Port 2
Port 5
Port 1
128
128
128
128
128
Result Bus
256
Quick PathInter-connect
DDR3MemoryController
CommonL3-Cache8 MByte
Uncore
4 x 20 Bit6,4 GT/s
3 x 64 Bit1,33 GT/s
GT/s: gigatransfers per second
Intel Nehalem microarchitecture